1. Field of the Invention
The present invention is related generally to a long interconnect between elements of an integrated circuit, and more particularly to an interconnect circuit capable of interrupting data transmission in a long interconnect responsive to congestion conditions.
2. Description of the Related Art
Due to recent advancements in large-scale integrated (LSI) circuit design and manufacturing technologies, the interconnect wires commonly used to connect LSI circuit elements have been steadily decreasing in size; currently, interconnect wires are as thin as about 0.2 microns (μm). In such a micro-wire, the wiring resistance may become as large as 300 ohms/mm, which creates difficulties with respect to high-speed transmission of data signals in the wire.
Such a high value of wiring resistance can be problematic, in particular, with respect to large-scale LSIs produced in recent years, in which the chip area has become large and the proportion of the connections on the chip requiring long interconnect wires, for example exceeding 10 mm in length, has increased.
For example, if wiring resistance, wiring capacity, output resistance of a driving circuit to activate the wire, and input capacity of the circuitry located at the output end, or “downstream” end, of the interconnect wire are assigned the symbols R1, C1, Rs, and C, respectively, the input/output delay time, or “latency,” of this interconnect wire is given by the formula:Rs*(C1+C)+R1*(C1/2+C) 
Given a long interconnect wire of 0 mm in length having typical values (for example, R1=3,000 ohms, C1=2,000 fF, Rs=370 ohms, and C=28 fF) for use in the next generation of LSIs (for example, a 0.1 μm-generation CMOS device), the latency of this 10 mm wire is about 3.8 ns.
Since the operational frequency of an LSI of this 0.1 μm-generation CMOS construction will generally exceed 1 GHz, this latency of 3.8 ns is quite a large value relative to the operational frequency.
In order to reduce on-chip interconnect latency caused by wiring resistance, it is common to insert repeaters (in the form of inverters or buffer amplifiers) at spaced intervals along an interconnect wire. Even with such inserted repeaters, however, interconnect latency increases with LSI process scaling, and this latency invariably degrades the performance of sophisticated LSIs.
Problems associated with interconnect latency can be greatly aggravated when the downstream end of a long interconnect is not capable of receiving data at the same rate at which the input end, or “upstream” end, of the interconnect is transmitting data. In present systems widely in use, when the downstream end of a long interconnect, due to congestion, for example, refuses to receive data signals which have been transmitted through the interconnect wire, a notice of this refusal is sent to the upstream end of the long interconnect. Thereupon, data input at the upstream end of the interconnect is temporarily interrupted. However, data in transit along the length of the interconnect may be lost; when the downstream end is not able to receive, it becomes necessary either to discard data within the interconnect, or to store that data temporarily until the downstream end is capable of resuming data reception. Such a data storage function is typically performed by one or more high capacity data buffers prepared separately at or near the downstream end of the long interconnect.
Also, when such a signal refusing data reception is delayed considerably in reaching the upstream end of the long interconnect (due to latency associated with the interconnect, for example), some data signals are transmitted during the latency period from the upstream end through the long interconnect uselessly; that is, the data signals, though transmitted from the upstream end, will never be received at the downstream end. In this situation, it becomes necessary to increase the capacity of the data buffers prepared at the downstream end of the long interconnect so that these data signals will not be lost; providing a long interconnect with high capacity data buffers is both expensive and inefficient.
Further, in conventional applications, since no valid data signals exist along the length of the long interconnect when the downstream end resumes data reception, there can be a significant delay (for example, as great as the latency of the entire long interconnect) for the first data signals to reach the downstream end after the resumption of data reception; such delays can produce a significant degradation in data transmission rates and overall throughput of the interconnect.
Consequently, simply adding inverters or buffer amplifiers at spaced intervals along the length of the interconnect, while reducing latency and increasing data throughput during the periods in which transmitted data signals are actually accepted at the downstream end, is not an adequate solution to the problems associated with data congestion in the interconnect.
Therefore, in creating the next generation high-performance large-scale LSIs, it is desirable to reduce the latency of a long interconnect while simultaneously addressing the problem of lost data which can occur due to congestion.